Power delivery in modern integrated circuit (IC) systems has become increasingly complex as supply voltages fall and power demands become more variant. A number of modern microprocessor systems, for example, require load voltage to be dynamically adjusted in response to processing demand, with voltage overshoot/undershoot to be maintained within closely specified ranges as load voltages change. IC-based power regulation and delivery systems have been developed to meet these requirements.
FIGS. 1A and 1B illustrate the structure and operation of a prior-art power-stage integrated circuit (IC) device 100 that may be used in an IC-based power delivery system. The power stage IC 100 includes a gate driver circuit 103 that alternately switches on a power transistor 105 and a bypass transistor 107 in response to a power-control signal (Pctrl). More specifically, when the control signal (Pctrl) goes high as shown by pulse 122, the power-stage IC 100 enters a power-delivery phase, or power phase, in which the gate driver 103 asserts a drive signal (Drv) as shown at 124 to switch the power transistor 105 to a conducting state, thereby enabling current to be delivered to a load RL after passing through a smoothing filter (low-pass filter) formed by inductor LF and capacitor CF. When, the control signal goes low, the gate driver 103 deasserts the drive signal, switching off the power transistor 105 and thus, decoupling the smoothing filter and load from voltage source, V+. A brief interval after the power transistor 105 is switched off, referred to herein as a dead time (130a) and provided to avoid the potential for shorting the V+ power supply to ground through transistor 107, the gate driver asserts a bypass signal (Byp) to switch the bypass transistor 107 to a conducting state and thus provide a low-resistance path for maintaining the load current through inductor LF until the next power phase. The interval in which the bypass transistor 107 is switched on (i.e., the bypass-signal assertion interval 126) is referred to herein as the bypass phase of the power-stage IC operation, and the current flowing through the inductor during this time is referred to as the bypass current. The bypass signal is deasserted for a second, brief dead-time interval 130b prior to the start of a subsequent power-delivery phase, again to avoid shorting the V+ supply to ground. Overall, the power phase, bypass phase, and interposed dead-time intervals constitute a power cycle of the power-stage IC and are repeated every switching period, TSWITCH. As more or less current is required by the load (i.e., in the case of a processing system, the demand for power may increase or decrease dramatically depending on processing needs), a controller (not shown in FIG. 1A) may adjust the duty cycle of the power control signal (i.e., increase the relative proportions of the switching period allocated to assertion of the drive signal and bypass signal) to enable more or less current to the load. Also, while a single power-stage IC is shown, multiple power-stage IC's may be provided, each to source power to the load during respective time-staggered power phases within each switching period.
As mentioned, the dead-time intervals 130a and 130b are provided to avoid shorting the V+ supply to ground during the transition between conduction phases of the power and bypass transistors 105 and 107. Unfortunately, though the dead-time intervals are brief, the bypass current is drawn through a relatively high-loss path of the body diode 109 formed between the source and drain of the bypass transistor 107. In a typical silicon-substrate power-stage IC, the cut-in voltage of the body diode 109 is approximately 0.6 volts so that the total power loss during the dead-time intervals 130a, 130b is the body-diode cut-in voltage, VBD, multiplied by the bypass current, IBYP. As the bypass current may be on the order of tens of amperes, this power dissipation in the device body may be substantial, resulting in significant wasted power. Aside from the loss of efficiency, the heat generation that results from power dissipation in the body diode may ultimately limit the maximum load current the power-stage IC may source.